The invention relates to a multi-chip system, more specifically to a multi-chip system including a volatile memory chip and a nonvolatile memory chip and a boot code fetch method.
Generally, the multi-chip system comprises volatile memory chips such as a DRAM, and nonvolatile memory chip such as a PROM, EPROM, EEPROM, SRAM, and a flash memory. The volatile memory chip loses stored data when a power supply is cut off. However, the nonvolatile memory chip maintains the data even when the power supply is cut off. Therefore, the nonvolatile memory chip is used as a storage of a basic input/output system (BIOS), a boot code, etc. in various application areas (e.g., a computer system) having a strong possibility of being cut off from the power supply.
One example of a multi-chip system including a DRAM chip and a NAND flash memory chip is illustrated in FIG. 1. Referring to FIG. 1, the multi-chip system 10 includes a host 100, a DRAM chip 200, a NAND flash memory chip 300, and a system bus 11. In this case, the NAND flash memory chip 300 is disclosed in “NAND flash memory and Smart Media”, on page 641 of a data book published by Samsung electronics. Co., Ltd. in September, 2003.
The host 100 includes a central processing unit 110 and a memory controller 111. The central processing unit (CPU) 110 fetches a boot code stored in the NAND flash memory chip 300 to perform an initialization operation at an initial power-up operation. The memory controller 111 controls entire operations of the DRAM chip 200 and the NAND flash memory chip 300. Especially, the memory controller 111 interfaces with a host interface unit 360 in the NAND flash memory chip 300, and provides various control signals (e.g., nCE, nOE, new, etc.) for the NAND flash memory chip 300.
The NAND flash memory chip 300 includes a NAND flash memory 310, a NAND flash interface unit 320, a bootRAM 330, a bootloader 350, and a host interface unit 360.
The NAND flash memory 310 comprises a large number of memory cells, and stores a boot code in a portion of the memory cells. The boot code stored in the NAND flash memory 310 is transferred to the bootRAM 330 via the NAND flash interface unit 320. The boot loader 350 provides a flash read command FR for the NAND flash interface unit 320, and a buffer write command BW for the bootRAM 330. In this case, the boot code stored in the NAND flash memory 310 is written in the bootRAM 330. Then, the bootloader 350 sends a buffer read command BR to the boot RAM 330. In this case, the boot code stored in the bootRAM 330 is transferred to the host 100 via the host interface unit 360.
In the multi-chip system 10, the host 100 fetches the boot code stored in the NAND flash memory chip 300 at an initial boot operation. In this case, the boot code should be fetched by the host 100 within a short time without a delay time. Therefore, the NAND flash memory chip 300 includes a bootRAM 330 having high operation speed. Before the host 100 fetches the boot code, the boot code is stored in the bootRAM 330. The host 100 is capable of performing the booting operation within a short time because the boot code is fetched in the bootRAM 330.
However, the bootRAM (e.g., an SRAM) 330 has a disadvantage of enlarging an area of the NAND flash memory chip 300. Because the bootRAM (e.g., an SRAM) 330 is in the NAND flash memory chip 300, it should be embodied as a design rule of the NAND flash memory. Therefore, the bootRAM 330 is larger than the SRAM in an area, so that an area of the NAND flash memory chip 300 is enlarged. Especially, as mobile systems tend to become more complicated, a size of the boot code increases. Therefore, the area increase of the bootRAM for storing the boot code becomes very burdensome, increasing design and manufacturing costs, and so on.